{"title":"Pentium/sup R/ III微处理器封装设计与性能评估","authors":"A. Sarangi, G. Ji, T. Arabi, G. Taylor","doi":"10.1109/EPEP.2001.967666","DOIUrl":null,"url":null,"abstract":"This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Design and performance evaluation of Pentium/sup R/ III microprocessor packaging\",\"authors\":\"A. Sarangi, G. Ji, T. Arabi, G. Taylor\",\"doi\":\"10.1109/EPEP.2001.967666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.\",\"PeriodicalId\":174339,\"journal\":{\"name\":\"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2001.967666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2001.967666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and performance evaluation of Pentium/sup R/ III microprocessor packaging
This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.
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