Optimal VLSI architecture for distributed arithmetic-based algorithms

Digital signal processing algorithms often use inner product as basic computation. In this paper we propose a new design methodology for synthesizing an optimal VLSI architecture implementing a real-time Distributed Arithmetic-based inner product. Our design methodology considers the design space as bidimensional one. In the first dimension we consider all possible input data parallelisations: from bit-serial to bit-parallel. In the second dimension we consider all possible lookup-table partitioning. Using a new ROM generic model, expressions are developed for area and maximum input data bandwidth, which allows to have an explicit formulation of the area-bandwidth tradeoff. Finally, for a given set of application constraints (inner product size and data bandwidth), we exhibit the optimal architectural parameters that provide the smallest chip area.<>