{"title":"一类用于半导体存储系统的系统t/ b错误校正码","authors":"G. Umanesan, E. Fujiwara","doi":"10.1109/ITW.2001.955144","DOIUrl":null,"url":null,"abstract":"This paper proposes a class of systematic codes called single t/B-error correcting - single b-bit byte error correcting - single b-bit block error detecting (S/sub t/B/EC-S/sub b/EC-S/sub B/ED) codes for high speed semiconductor memory systems. The proposed codes correct multiple random t-bit errors occurring within a chip and b-bit byte errors caused by sub-array data faults while simultaneously indicating B-bit block errors caused by complete chip failures.","PeriodicalId":288814,"journal":{"name":"Proceedings 2001 IEEE Information Theory Workshop (Cat. No.01EX494)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A class of systematic t/B-error correcting codes for semiconductor memory systems\",\"authors\":\"G. Umanesan, E. Fujiwara\",\"doi\":\"10.1109/ITW.2001.955144\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a class of systematic codes called single t/B-error correcting - single b-bit byte error correcting - single b-bit block error detecting (S/sub t/B/EC-S/sub b/EC-S/sub B/ED) codes for high speed semiconductor memory systems. The proposed codes correct multiple random t-bit errors occurring within a chip and b-bit byte errors caused by sub-array data faults while simultaneously indicating B-bit block errors caused by complete chip failures.\",\"PeriodicalId\":288814,\"journal\":{\"name\":\"Proceedings 2001 IEEE Information Theory Workshop (Cat. No.01EX494)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-09-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 2001 IEEE Information Theory Workshop (Cat. No.01EX494)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITW.2001.955144\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 IEEE Information Theory Workshop (Cat. No.01EX494)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITW.2001.955144","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A class of systematic t/B-error correcting codes for semiconductor memory systems
This paper proposes a class of systematic codes called single t/B-error correcting - single b-bit byte error correcting - single b-bit block error detecting (S/sub t/B/EC-S/sub b/EC-S/sub B/ED) codes for high speed semiconductor memory systems. The proposed codes correct multiple random t-bit errors occurring within a chip and b-bit byte errors caused by sub-array data faults while simultaneously indicating B-bit block errors caused by complete chip failures.
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