A system design for UHF RFID reader

This paper introduces a system design for RFID reader. The RFID reader is compatible with EPC Class-1, Generation-2 Standard, operating at the 915 MHz band. The UHF RFID reader includes RF analog front end (AFE), the base band design and clock control. The RFID RF AFE contains transmitting circuit, receiving circuit, frequency synthesize, circulator, etc. The base band contains the FPGA chip, 100 M hardware resources of network supporting, DDR SDRAM, FLASH, A/D, D/A, etc. The FPGA chip inseted NiosII soft core. This architecture is an advantage for implementing various kinds of RFID standards by changing the soft of NiosII core in FPGA, and efficiently reduces the design and development time and cost.