{"title":"带进位移位寄存器的斐波那契和伽罗瓦模式反馈","authors":"M. Goresky, A. Klapper","doi":"10.1109/ISIT.2001.935957","DOIUrl":null,"url":null,"abstract":"A feedback-with-carry shift register (FCSR) with \"Fibonacci\" architecture is a shift register provided with a small amount of memory which is used in the feedback algorithm. Like linear feedback shift registers (LFSRs), FCSRs provide a simple and predictable method for the fast generation of pseudorandom sequences with good statistical properties and large periods. We analyze an alternative architecture for FCSRs which is similar to the \"Galois\" architecture for LFSRs. We also describe the output sequences generated by d-FCSRs, a slight modification of the (Fibonacci) FCSR architecture in which the feedback bit is delayed for d clock cycles before being returned to the first cell of the shift register. We show that d-FCSRs also admit a more efficient \"Galois\" architecture.","PeriodicalId":433761,"journal":{"name":"Proceedings. 2001 IEEE International Symposium on Information Theory (IEEE Cat. No.01CH37252)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Fibonacci and Galois mode feedback with carry shift registers\",\"authors\":\"M. Goresky, A. Klapper\",\"doi\":\"10.1109/ISIT.2001.935957\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A feedback-with-carry shift register (FCSR) with \\\"Fibonacci\\\" architecture is a shift register provided with a small amount of memory which is used in the feedback algorithm. Like linear feedback shift registers (LFSRs), FCSRs provide a simple and predictable method for the fast generation of pseudorandom sequences with good statistical properties and large periods. We analyze an alternative architecture for FCSRs which is similar to the \\\"Galois\\\" architecture for LFSRs. We also describe the output sequences generated by d-FCSRs, a slight modification of the (Fibonacci) FCSR architecture in which the feedback bit is delayed for d clock cycles before being returned to the first cell of the shift register. We show that d-FCSRs also admit a more efficient \\\"Galois\\\" architecture.\",\"PeriodicalId\":433761,\"journal\":{\"name\":\"Proceedings. 2001 IEEE International Symposium on Information Theory (IEEE Cat. No.01CH37252)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 2001 IEEE International Symposium on Information Theory (IEEE Cat. No.01CH37252)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISIT.2001.935957\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 2001 IEEE International Symposium on Information Theory (IEEE Cat. No.01CH37252)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISIT.2001.935957","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fibonacci and Galois mode feedback with carry shift registers
A feedback-with-carry shift register (FCSR) with "Fibonacci" architecture is a shift register provided with a small amount of memory which is used in the feedback algorithm. Like linear feedback shift registers (LFSRs), FCSRs provide a simple and predictable method for the fast generation of pseudorandom sequences with good statistical properties and large periods. We analyze an alternative architecture for FCSRs which is similar to the "Galois" architecture for LFSRs. We also describe the output sequences generated by d-FCSRs, a slight modification of the (Fibonacci) FCSR architecture in which the feedback bit is delayed for d clock cycles before being returned to the first cell of the shift register. We show that d-FCSRs also admit a more efficient "Galois" architecture.