{"title":"为弹性捆绑数据设计添加条件性","authors":"D. Hand, A. Katrin, W. Koven","doi":"10.1109/ASYNC.2016.22","DOIUrl":null,"url":null,"abstract":"We describe a practical method of generating production ready timing violation resilient asynchronous circuits with conditional communication from a high level hardware description language. Designs written in SystemVerilogCSP are taped out on a 3.3 million transistor chip. We present two slackless scan-enabled asynchronous controllers based on the Click template that saved an average area of 14% in our application.","PeriodicalId":314538,"journal":{"name":"2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Adding Conditionality to Resilient Bundled-Data Designs\",\"authors\":\"D. Hand, A. Katrin, W. Koven\",\"doi\":\"10.1109/ASYNC.2016.22\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe a practical method of generating production ready timing violation resilient asynchronous circuits with conditional communication from a high level hardware description language. Designs written in SystemVerilogCSP are taped out on a 3.3 million transistor chip. We present two slackless scan-enabled asynchronous controllers based on the Click template that saved an average area of 14% in our application.\",\"PeriodicalId\":314538,\"journal\":{\"name\":\"2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASYNC.2016.22\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.2016.22","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Adding Conditionality to Resilient Bundled-Data Designs
We describe a practical method of generating production ready timing violation resilient asynchronous circuits with conditional communication from a high level hardware description language. Designs written in SystemVerilogCSP are taped out on a 3.3 million transistor chip. We present two slackless scan-enabled asynchronous controllers based on the Click template that saved an average area of 14% in our application.
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