A new shift-register based ATM switch

In this paper, we introduce a new ATM switch architecture. The proposed design takes the best features of input, output and shared buffers schemes. Furthermore, buffer access speeds match the port speeds and the buffer acts in effect, as a multiport memory. The input buffers are implemented as a group of parallel shift registers. The parallel shift registers overcome the HOL and low throughput problems of input buffers. The use of shift register buffers allows operating speeds much higher than is possible using RAM buffers. Furthermore, switch speed is independent of buffer size. This is a very important feature for ATM networks that require storage of large amounts of cells in the switching nodes. The parallel nature of the input queues simplifies the supporting of multicast functions. In addition, the modularity of the proposed architecture facilitates its scalability.