Trace-driven simulations for a two-level cache design of open bus systems

Two-level cache hierarchies will be a design issue in future high-performance CPUs. An evaluation is made of various metrics for data cache designs. A discussion is presented of one- and two-level cache hierarchies. The target is a new 100+ MIPS CPU, but the methods are applicable to any cache design. The basis of this work is a new trace-driven, multiprocess cache simulator. The simulator incorporates a simple priority-based scheduler which controls the execution of the processes. The scheduler blocks a process when a system call is executed. A workload consists of a total of 60 processes, distributed among seven unique programs with about nine instances each. Two open bus systems, Futurebus+ and Scalable Coherent Interface (SCI), that support a coherent memory model, are discussed as the interconnect system for main memory.<>