Implementation of recurrent neural network algorithm for shortest path calculation in network routing

This paper describes the architecture and implementation of a shortest-path processor, both in reconfigurable hardware and VLSI. This processor is based on the principles of a recurrent spatiotemporal neural network. The processor's operation is similar to E.W. Dijkstra's (1959) algorithm and it can be used for network routing calculations. The objective of the processor is to find the least-cost path in a weighted graph between a given node and one or more destinations. The digital implementation, which exhibits a regular interconnect structure and uses simple processing elements, is well-suited for VLSI implementation and reconfigurable hardware.