一种收缩式集成电路整数除法器

J. Eldon
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引用次数: 2

摘要

提出了一种低功耗、高速、高性价比的整数除法器TMC3211 cmos集成电路。TMC3211以每秒2500万次运算的速度处理32位的股利和16位的除数,并返回32位的商。TMC3211被实现为由16个相同的两块算术单元组成的一维收缩数组,每个单元接受股利的下两位并生成商的下两位,同时将其余数和原始除数传递给序列中的下一个单元。
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A systolic integrated circuit integer divider
The TMC3211 CMOS-integrated circuit integer divider, which offers a low-power, high-speed, cost-effective solution to the division problem, is presented. Operating on 32-bit dividends and 16-bit divisors and returning 32-bit quotients at 25 million operations per second, the TMC3211 is implemented as a one-dimensional systolic array of 16 identical two-block arithmetic cells, each of which accepts the next two bits of the dividend and generates the next two bits of the quotient, while passing its remainder and the original divisor to the next cell in the series.<>
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