{"title":"基于噪声传递函数评估的高分辨率SD ADC新测试途径","authors":"D. Venuto","doi":"10.1109/ISQED.2004.1283654","DOIUrl":null,"url":null,"abstract":"A new solution to improve the testability of high resolution /spl Sigma//spl Delta/ analogue to digital converters (/spl Sigma//spl Delta/ ADCs) using the quantizer input as a test node is described. Both the theory of the method and results from high level simulations for a 16 bit audio ADC example are presented. The analysis demonstrates the potential to reduce the computation overhead associated with test response analysis versus conventional techniques.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"New Test Access for High Resolution SD ADC's by Using the Noise Transfer Function Evaluation\",\"authors\":\"D. Venuto\",\"doi\":\"10.1109/ISQED.2004.1283654\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new solution to improve the testability of high resolution /spl Sigma//spl Delta/ analogue to digital converters (/spl Sigma//spl Delta/ ADCs) using the quantizer input as a test node is described. Both the theory of the method and results from high level simulations for a 16 bit audio ADC example are presented. The analysis demonstrates the potential to reduce the computation overhead associated with test response analysis versus conventional techniques.\",\"PeriodicalId\":302936,\"journal\":{\"name\":\"IEEE International Symposium on Quality Electronic Design\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2004.1283654\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2004.1283654","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
New Test Access for High Resolution SD ADC's by Using the Noise Transfer Function Evaluation
A new solution to improve the testability of high resolution /spl Sigma//spl Delta/ analogue to digital converters (/spl Sigma//spl Delta/ ADCs) using the quantizer input as a test node is described. Both the theory of the method and results from high level simulations for a 16 bit audio ADC example are presented. The analysis demonstrates the potential to reduce the computation overhead associated with test response analysis versus conventional techniques.
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