{"title":"DVB-S2中LDPC码的设计与实现","authors":"M. Yadav, K. K. Parhi","doi":"10.1109/ACSSC.2005.1599847","DOIUrl":null,"url":null,"abstract":"In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design and Implementation of LDPC Codes for DVB-S2\",\"authors\":\"M. Yadav, K. K. Parhi\",\"doi\":\"10.1109/ACSSC.2005.1599847\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA\",\"PeriodicalId\":326489,\"journal\":{\"name\":\"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.2005.1599847\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.2005.1599847","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Implementation of LDPC Codes for DVB-S2
In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA
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