High speed binary addition

Addition of two binary numbers is a fundamental operation in electronic circuits. Applications include arithmetic logic unit, floating-point operations and address generation. It is widely accepted that there is no single best adder implementation. Modern adder architectures utilize a hybrid scheme based on, among others, various parallel prefix, carry select and Ling architectures. The parallel prefix method implements logic functions which determine whether groups of bits will generate or propagate a carry. These functions are hierarchically combined to calculate the carry into any bit. Ling adders reduce delay by using a simplified version of the group generates. However, the method only reduces complexity at the first level; all subsequent combinations in the hierarchy have the same complexity as the parallel prefix method. In this article we present novel architectures, which have reduced complexity at all, levels.