{"title":"优化一个超标量机器来运行矢量代码","authors":"S. Weiss","doi":"10.1109/88.218177","DOIUrl":null,"url":null,"abstract":"A streamlined vector architecture and the IBM superscalar RISC System/6000 are discussed. It is shown, step-by-step, how each handles the same program. The factors that let vector machines outperform the RS/6000 are identified. Several extensions to the RS/6000 architecture that could help it attain vector-level performance on code with long vectors are proposed.<<ETX>>","PeriodicalId":325213,"journal":{"name":"IEEE Parallel & Distributed Technology: Systems & Applications","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Optimizing a superscalar machine to run vector code\",\"authors\":\"S. Weiss\",\"doi\":\"10.1109/88.218177\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A streamlined vector architecture and the IBM superscalar RISC System/6000 are discussed. It is shown, step-by-step, how each handles the same program. The factors that let vector machines outperform the RS/6000 are identified. Several extensions to the RS/6000 architecture that could help it attain vector-level performance on code with long vectors are proposed.<<ETX>>\",\"PeriodicalId\":325213,\"journal\":{\"name\":\"IEEE Parallel & Distributed Technology: Systems & Applications\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Parallel & Distributed Technology: Systems & Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/88.218177\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Parallel & Distributed Technology: Systems & Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/88.218177","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimizing a superscalar machine to run vector code
A streamlined vector architecture and the IBM superscalar RISC System/6000 are discussed. It is shown, step-by-step, how each handles the same program. The factors that let vector machines outperform the RS/6000 are identified. Several extensions to the RS/6000 architecture that could help it attain vector-level performance on code with long vectors are proposed.<>