Simulation Method of Ultra-Thin Silicon Wafers Warpage

As the electronic products, such as smart phones, notebooks, and micro-control parts for vehicles, are becoming increasingly popular and their size continues do decrease, there is also a need to reduce the volume of ultra-thin silicon wafers while improving their performance. At present, backside grinding is typically used for this purpose, and requires that the wafer is placed on the chuck of a self-rotating wheel, while controlling the feed rate in order to reduce wafer thickness. Although this process is efficient and effective, it may result in subsurface damage, surface cracks, micro-cracks, warpage, and other undesirable effects. One of its main drawbacks is residual stress, which becomes more pronounced in very thin wafers, as this increases rigidity. Stoney equation is widely used to examine the residual stress and curvature radius in a silicon wafer due to the backside grinding process. However, the relationship between the residual stress generated in the wafer during the grinding process and the process parameters is rarely analyzed through simulations. This gap is addressed in the present study, whereby the finite element method (FEM) is adopted to examine the effects of different process parameters, as well as wafer thickness, on the residual stress. As dynamic simulation is adopted, this allows the process parameters to be adjusted at runtime to predict the residual stress, while Stoney’s equation is employed to predict the influence of different process parameters on warpage. Based on the obtained results, the wafer warpage caused by the process can be predicted with acceptable accuracy, which can in turn be used to optimize the process parameter values to minimize wafer warpage.