{"title":"TDD:基于lut的fpga的技术相关分解算法","authors":"A. Farrahi, M. Sarrafzadeh","doi":"10.1109/ASIC.1997.617006","DOIUrl":null,"url":null,"abstract":"A major drawback of the previous algorithms that perform decomposition and covering for LUT-based FPGA technology mapping is the lack of a fast, and reasonably accurate evaluation scheme for the decomposition phase. In this paper, we will show how a fast covering algorithm can be used as an evaluation engine for the decomposition phase. We show that decomposition has a significant impact on the quality of the final mapping result. More specifically, we show that starting from the same circuit topology, a blind decomposition leads to mapping results that use an average of 70 to 150% more LUTs compared to the results obtained using a technology driven decomposition algorithm. A technology driven decomposition algorithm is developed based on the proposed idea. Experiments on a number of MCNC benchmark circuits show an average of 12% to 72% improvement on the number of LUTs compared to the previously reported results.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"TDD: a technology dependent decomposition algorithm for LUT-based FPGAs\",\"authors\":\"A. Farrahi, M. Sarrafzadeh\",\"doi\":\"10.1109/ASIC.1997.617006\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A major drawback of the previous algorithms that perform decomposition and covering for LUT-based FPGA technology mapping is the lack of a fast, and reasonably accurate evaluation scheme for the decomposition phase. In this paper, we will show how a fast covering algorithm can be used as an evaluation engine for the decomposition phase. We show that decomposition has a significant impact on the quality of the final mapping result. More specifically, we show that starting from the same circuit topology, a blind decomposition leads to mapping results that use an average of 70 to 150% more LUTs compared to the results obtained using a technology driven decomposition algorithm. A technology driven decomposition algorithm is developed based on the proposed idea. Experiments on a number of MCNC benchmark circuits show an average of 12% to 72% improvement on the number of LUTs compared to the previously reported results.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617006\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617006","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
TDD: a technology dependent decomposition algorithm for LUT-based FPGAs
A major drawback of the previous algorithms that perform decomposition and covering for LUT-based FPGA technology mapping is the lack of a fast, and reasonably accurate evaluation scheme for the decomposition phase. In this paper, we will show how a fast covering algorithm can be used as an evaluation engine for the decomposition phase. We show that decomposition has a significant impact on the quality of the final mapping result. More specifically, we show that starting from the same circuit topology, a blind decomposition leads to mapping results that use an average of 70 to 150% more LUTs compared to the results obtained using a technology driven decomposition algorithm. A technology driven decomposition algorithm is developed based on the proposed idea. Experiments on a number of MCNC benchmark circuits show an average of 12% to 72% improvement on the number of LUTs compared to the previously reported results.