{"title":"高效可重构网络的设计","authors":"Arun Kumar Somani","doi":"10.1109/IPPS.1993.262918","DOIUrl":null,"url":null,"abstract":"The author presents a methodology to design an efficient communication reconfigurable network of processor using a circuit switching environment. He assumes that the operation is synchronous and reconfigurations occur at pre-specified times. This network is based on two architectural concepts, the generalized folding cube and the enhanced hypercube architectures. The author demonstrates the effectiveness, versatility, and flexibility of his approach.<<ETX>>","PeriodicalId":248927,"journal":{"name":"[1993] Proceedings Seventh International Parallel Processing Symposium","volume":"3 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of efficient reconfigurable networks\",\"authors\":\"Arun Kumar Somani\",\"doi\":\"10.1109/IPPS.1993.262918\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The author presents a methodology to design an efficient communication reconfigurable network of processor using a circuit switching environment. He assumes that the operation is synchronous and reconfigurations occur at pre-specified times. This network is based on two architectural concepts, the generalized folding cube and the enhanced hypercube architectures. The author demonstrates the effectiveness, versatility, and flexibility of his approach.<<ETX>>\",\"PeriodicalId\":248927,\"journal\":{\"name\":\"[1993] Proceedings Seventh International Parallel Processing Symposium\",\"volume\":\"3 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1993] Proceedings Seventh International Parallel Processing Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPPS.1993.262918\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993] Proceedings Seventh International Parallel Processing Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPPS.1993.262918","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The author presents a methodology to design an efficient communication reconfigurable network of processor using a circuit switching environment. He assumes that the operation is synchronous and reconfigurations occur at pre-specified times. This network is based on two architectural concepts, the generalized folding cube and the enhanced hypercube architectures. The author demonstrates the effectiveness, versatility, and flexibility of his approach.<>
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