An asynchronous 2-D discrete cosine transform chip

This paper describes a fully asynchronous two-dimensional discrete cosine transform chip. The chip has a fixed block size of 8/spl times/8 pixels and uses bit-serial arithmetic. The chip was fabricated through MOSIS using a 0.8 /spl mu/ double-metal CMOS process. The 49.5 mm/sup 2/ core uses /spl sim/162,000 transistors. The chip operates from 0.65 V to 7.0 V, but its pixel rate at 5.0 V, 17 MHz, is significantly below the 27 MHz simulated because none of the signal's capacitances were backextracted. In order to design a completely asynchronous chip, a FIFO-based transposition memory was used, even though it used more area than RAM-based memory. The most interesting aspects of the design are presented here: the memory control structure, the pipelining structures, the use of Xilinx FPGAs and a Quickturn emulation system for emulation, and a comparison with other synchronous and asynchronous designs.