High performance dual gate GNR fet

The scaling of CMOS technology has progressed rapidly for three decades. But CMOS is bound to reach its limits due to certain constraints such as minimum dimensions that can be fabricated, degradation in switching performance, power-dissipation etc. Thus, the technologies that may replace CMOS when the limit is reached need to be investigated. Some of the potential solutions can be use of new materials such as graphene or new structures such as Dual gate and back gate. In this paper we investigate the structural and electronic properties of graphene nano-ribbons when devised into dual gate and back-gate structures. Simulation results have been used to support the paper.