{"title":"基于ca的双字节纠错编解码器体系结构设计","authors":"J. Bhaumik, Balaji Janakiram, D. R. Chowdhury","doi":"10.1109/ICIINFS.2008.4798442","DOIUrl":null,"url":null,"abstract":"Cellular Automata (CA) is a novel approach for designing byte error-correcting codes. The regular, modular and cascaded structure of CA can be economically built with VLSI technology. In this correspondence, a modular architecture of CA based (32, 28) byte error correcting encoder and decoder has been proposed. The design is capable of locating and correcting all double byte errors. CA-based implementation of the proposed decoding scheme provides a simple cost effective solution compared to the existing decoding scheme for the Reed-Solomon (RS) decoder, having double error correcting capability.","PeriodicalId":429889,"journal":{"name":"2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Architectural Design of CA-Based Double Byte Error Correcting Codec\",\"authors\":\"J. Bhaumik, Balaji Janakiram, D. R. Chowdhury\",\"doi\":\"10.1109/ICIINFS.2008.4798442\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cellular Automata (CA) is a novel approach for designing byte error-correcting codes. The regular, modular and cascaded structure of CA can be economically built with VLSI technology. In this correspondence, a modular architecture of CA based (32, 28) byte error correcting encoder and decoder has been proposed. The design is capable of locating and correcting all double byte errors. CA-based implementation of the proposed decoding scheme provides a simple cost effective solution compared to the existing decoding scheme for the Reed-Solomon (RS) decoder, having double error correcting capability.\",\"PeriodicalId\":429889,\"journal\":{\"name\":\"2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIINFS.2008.4798442\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIINFS.2008.4798442","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Architectural Design of CA-Based Double Byte Error Correcting Codec
Cellular Automata (CA) is a novel approach for designing byte error-correcting codes. The regular, modular and cascaded structure of CA can be economically built with VLSI technology. In this correspondence, a modular architecture of CA based (32, 28) byte error correcting encoder and decoder has been proposed. The design is capable of locating and correcting all double byte errors. CA-based implementation of the proposed decoding scheme provides a simple cost effective solution compared to the existing decoding scheme for the Reed-Solomon (RS) decoder, having double error correcting capability.
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