ASIC design of MIPS based RISC processor for high performance

Objectives: The main aim of this paper is to implement 32Bit MIPS (Microprocessor Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using Verilog HDL (hardware description language). Methods/Statistical analysis: The proposed algorithm analyzes the different stages of instruction decoding such as Instruction fetch module, Decoder module, Execution module and design theory based on 32Bit MIPS RISC Processor. In addition to that the algorithm uses pipelining concept which involves Instruction Fetch, Instruction Decode, Execution, Memory and Write Back modules of MIPS RISC processor based on 32Bit MIPS Instruction set in a single clock cycle. Findings: RISC is a processor which is intended to perform a tiny set of operations, to expand the rate (speed) of the processor. In general, the processor works with a huge number of instructions every second by bringing the information from the memory. In the event that the processor speed does not coordinate with memory access speed then hardware interlocks happen. In concurring with this there is one more issue called stalls because of instruction pipelining in the CPU design. The primary desire of this paper is to design and synthesize the MIPS processor by making utilization of register files and to insert the ALU forwarding unit in order to avoid the stalls and hardware interlocks. Application/Improvements: Based on the literature survey, the proposed method brings significant power efficiency improvements with enhanced performance and reduced power dissipation due to not only technology scaling but also a great deal of design efforts.