{"title":"一个GaAs IEEE浮点标准单精度乘法器","authors":"S. Cui, N. Burgess, M. Liebelt, K. Eshraghian","doi":"10.1109/ARITH.1995.465372","DOIUrl":null,"url":null,"abstract":"This paper presents a GaAs IEEE floating point standard single precision multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and compact layout style achieves 4 ns multiplication time with 3.5 W power dissipation at 75/spl deg/C giving 14 mW/MHz. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28,000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8-/spl mu/m GaAs technology.<<ETX>>","PeriodicalId":332829,"journal":{"name":"Proceedings of the 12th Symposium on Computer Arithmetic","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1995-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A GaAs IEEE floating point standard single precision multiplier\",\"authors\":\"S. Cui, N. Burgess, M. Liebelt, K. Eshraghian\",\"doi\":\"10.1109/ARITH.1995.465372\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a GaAs IEEE floating point standard single precision multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and compact layout style achieves 4 ns multiplication time with 3.5 W power dissipation at 75/spl deg/C giving 14 mW/MHz. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28,000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8-/spl mu/m GaAs technology.<<ETX>>\",\"PeriodicalId\":332829,\"journal\":{\"name\":\"Proceedings of the 12th Symposium on Computer Arithmetic\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 12th Symposium on Computer Arithmetic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1995.465372\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 12th Symposium on Computer Arithmetic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1995.465372","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A GaAs IEEE floating point standard single precision multiplier
This paper presents a GaAs IEEE floating point standard single precision multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and compact layout style achieves 4 ns multiplication time with 3.5 W power dissipation at 75/spl deg/C giving 14 mW/MHz. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28,000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8-/spl mu/m GaAs technology.<>