Peter K. Jeffery, David K Ford, Peter P. Pham, M. C. Reed, Nandini Srinivasan, B. Weir
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The architecture, logic, and circuit design of a bipolar, 200 Mbyte/sec, serializing data mover IC, with 32-bit TTL-compatible parallel I/O and unique 1.8 Gbit/sec 'cutoff driver' differential PECL serial I/O
This paper discusses the architecture, logic design, and circuit design of the Autobahn Spanceiver-a serializing transceiver IC that facilitates movement of arbitrarily large blocks of 32-bit parallel TTL data at data rates up to 200 MBytes/sec, between two or more nodes on a shared, controlled-impedance, half-duplex, 1.8 Gbit/sec, differential-PECL serial channel.
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