{"title":"VAX硬件为建议的IEEE浮点标准","authors":"G. Taylor, D. Patterson","doi":"10.1109/ARITH.1981.6159294","DOIUrl":null,"url":null,"abstract":"The proposed IEEE floating-point standard has been implemented in a substitute floating-point accelerator for the VAX∗∗ 11/780. We explain how features of the proposed standard influenced the design of the new processor. By comparing it with the original VAX accelerator, we illustrate the differences between hardware for the proposed standard and hardware for a more traditional floating-point architecture.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"VAX hardware for the proposed IEEE floating-point standard\",\"authors\":\"G. Taylor, D. Patterson\",\"doi\":\"10.1109/ARITH.1981.6159294\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The proposed IEEE floating-point standard has been implemented in a substitute floating-point accelerator for the VAX∗∗ 11/780. We explain how features of the proposed standard influenced the design of the new processor. By comparing it with the original VAX accelerator, we illustrate the differences between hardware for the proposed standard and hardware for a more traditional floating-point architecture.\",\"PeriodicalId\":169426,\"journal\":{\"name\":\"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)\",\"volume\":\"107 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1981-05-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1981.6159294\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1981.6159294","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
VAX hardware for the proposed IEEE floating-point standard
The proposed IEEE floating-point standard has been implemented in a substitute floating-point accelerator for the VAX∗∗ 11/780. We explain how features of the proposed standard influenced the design of the new processor. By comparing it with the original VAX accelerator, we illustrate the differences between hardware for the proposed standard and hardware for a more traditional floating-point architecture.