Innovative techniques in comparator designs

This paper studies five innovative designs of comparators proposed these years. The dynamic bias comparator ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator with a floating inverter amplifier (FIA)-based pre-amplifier realizes the stability of input common-mode voltage and reduces influence of the process corner, moreover, thereby greatly boosting gm/ID and reduce noise, offset and delay. The edgepursuit comparator (EPC) has unique ability to adapt energy cost automatically, it can provide a new idea for the design of comparator. Triple-latch feedforward dynamic comparator (TLFF) with minimized stacking achieved < 70-ps delay in a wide common-mode (VCM) and power supply (VDD) range, and with the increase of input voltage, its delay advantage is more obvious. Low-Power High-Speed Dynamic Comparator in the evaluation phase, the latch reduces energy consumption and delay by delaying activation and using small cross-coupled transistors