Error Detection and Recovery in FPGA-based Pipelined Architectures

In safety-critical applications, it is very important for the system to be very reliable. This paper focuses on such applications when implemented with pipelined architectures on SRAM-based FPGAs. The fault model consists of Hard Faults and Single Event Upsets (SEUs). Three different architectures are proposed to add fault detection and/or recovery in order to increase system reliability. It is shown that these improvements are made at a small cost in terms of area, power consumption and performance. An Altera Cyclone IV E FPGA is used to explain the design and the architectures’ behaviors while Markov models are used to calculate reliability increase.