Protecting partial regions in FPGA bitstreams

In previous generations of Intel FPGAs, we employed design separation through the use of LogicLock in Cyclone IIILS and Arria V devices. In the past, this meant separation of design elements as well as designated protected design boundaries in different ‘Logic Lock’ regions. Though separated logically, these regions have the same protection and risk if the key is revealed. Today, using Partition-Based Security, we can encrypt these regions with different keys thus fully supporting separation and allowing secure, encrypted regions of the FPGA fabric to exist. We demonstrate partition-based security using an Intel FPGA Arria 10 SoC Development Kit with two partial reconfiguration regions encrypted with two different keys.