{"title":"基于在线算法的多层感知器反向传播的可编程硬件实现","authors":"B. Girau, Arnaud Tisserand","doi":"10.1109/MNNFS.1996.493788","DOIUrl":null,"url":null,"abstract":"A digital hardware implementation of a whole neural network learning is described. It uses on-line arithmetic on FPGAs. The modularity of our solution avoids the development problems that occur with more usual hardware circuits. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"979 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"On-line arithmetic-based reprogrammable hardware implementation of multilayer perceptron back-propagation\",\"authors\":\"B. Girau, Arnaud Tisserand\",\"doi\":\"10.1109/MNNFS.1996.493788\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digital hardware implementation of a whole neural network learning is described. It uses on-line arithmetic on FPGAs. The modularity of our solution avoids the development problems that occur with more usual hardware circuits. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation.\",\"PeriodicalId\":151891,\"journal\":{\"name\":\"Proceedings of Fifth International Conference on Microelectronics for Neural Networks\",\"volume\":\"979 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Fifth International Conference on Microelectronics for Neural Networks\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MNNFS.1996.493788\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNNFS.1996.493788","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-line arithmetic-based reprogrammable hardware implementation of multilayer perceptron back-propagation
A digital hardware implementation of a whole neural network learning is described. It uses on-line arithmetic on FPGAs. The modularity of our solution avoids the development problems that occur with more usual hardware circuits. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation.
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