ON current improvement techniques for double gate-tunnel field effect transistor

The present design describes the behavior of drain current of DG-TFET with different parameter like gate insulator dielectric, its thickness and silicon body thickness. An improved ON current is archived using optimized device parameter, ON current as high as 0.18 mA and off current of the order of 10−19 A have been archived and a instantaneous sub threshold slope of as low as 16 mV/dec has been observed which is one of the reason why TFET could replace MOSFET. The simulation has been carried out with non-local barrier tunneling model using Synopsys TCAD Tool. A Huge ION/Ioff ratio of more than1014 is obtained for 50 nm channel length DG-TFET. So Tunnel FET can be a promising candidate for low-standby low-power switching performance.