{"title":"通过在单个程序中分配资源来衡量硬件效率","authors":"J. Linn","doi":"10.1145/503506.503518","DOIUrl":null,"url":null,"abstract":"A view of efficiency is proposed which tries to account for how much resource is used in the actual problem solution and how much in the control of the instruction stream. Analyses are performed to determine the effects of two architectural modifications -- cache memory and memory mapped registers -- on the efficiency of a simple list merging process.","PeriodicalId":258426,"journal":{"name":"ACM-SE 17","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Measuring hardware efficiency by distribution of resources within a single program\",\"authors\":\"J. Linn\",\"doi\":\"10.1145/503506.503518\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A view of efficiency is proposed which tries to account for how much resource is used in the actual problem solution and how much in the control of the instruction stream. Analyses are performed to determine the effects of two architectural modifications -- cache memory and memory mapped registers -- on the efficiency of a simple list merging process.\",\"PeriodicalId\":258426,\"journal\":{\"name\":\"ACM-SE 17\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1979-04-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ACM-SE 17\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/503506.503518\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM-SE 17","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/503506.503518","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Measuring hardware efficiency by distribution of resources within a single program
A view of efficiency is proposed which tries to account for how much resource is used in the actual problem solution and how much in the control of the instruction stream. Analyses are performed to determine the effects of two architectural modifications -- cache memory and memory mapped registers -- on the efficiency of a simple list merging process.
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