M. Marin, F. Constantinescu, Catalin Brinzei, A. Gheorghe
{"title":"一种数模转换器校准方法的验证","authors":"M. Marin, F. Constantinescu, Catalin Brinzei, A. Gheorghe","doi":"10.1109/ISFEE.2016.7803193","DOIUrl":null,"url":null,"abstract":"A new calibration method for digital to analog converters (DAC) is verified, measuring a set of chips, each containing a 8 bit current steering DAC with a 5+3 segmented architecture. For a sampling frequency of 500MHz and a bandwidth of 5MHz all tested circuits exhibited, after calibration, a Spurious Free Dynamic Range (SFDR) better than 50dB. For a sampling frequency of 1GHz and a bandwidth of 10MHz, a SFDR better than 40dB resulted for all tested cases. These last results could be explained by a degradation of the digital signal supplied by the FPGA board, which has a maximum reliable clock frequency of 600MHz, and by the influence of the parasitic elements introduced by the PCB traces. In all measured cases an improvement of 2-4dB of the SFDR value has been obtained using the proposed calibration method.","PeriodicalId":240170,"journal":{"name":"2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Verification of a calibration method for digital to analog converters\",\"authors\":\"M. Marin, F. Constantinescu, Catalin Brinzei, A. Gheorghe\",\"doi\":\"10.1109/ISFEE.2016.7803193\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new calibration method for digital to analog converters (DAC) is verified, measuring a set of chips, each containing a 8 bit current steering DAC with a 5+3 segmented architecture. For a sampling frequency of 500MHz and a bandwidth of 5MHz all tested circuits exhibited, after calibration, a Spurious Free Dynamic Range (SFDR) better than 50dB. For a sampling frequency of 1GHz and a bandwidth of 10MHz, a SFDR better than 40dB resulted for all tested cases. These last results could be explained by a degradation of the digital signal supplied by the FPGA board, which has a maximum reliable clock frequency of 600MHz, and by the influence of the parasitic elements introduced by the PCB traces. In all measured cases an improvement of 2-4dB of the SFDR value has been obtained using the proposed calibration method.\",\"PeriodicalId\":240170,\"journal\":{\"name\":\"2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISFEE.2016.7803193\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISFEE.2016.7803193","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Verification of a calibration method for digital to analog converters
A new calibration method for digital to analog converters (DAC) is verified, measuring a set of chips, each containing a 8 bit current steering DAC with a 5+3 segmented architecture. For a sampling frequency of 500MHz and a bandwidth of 5MHz all tested circuits exhibited, after calibration, a Spurious Free Dynamic Range (SFDR) better than 50dB. For a sampling frequency of 1GHz and a bandwidth of 10MHz, a SFDR better than 40dB resulted for all tested cases. These last results could be explained by a degradation of the digital signal supplied by the FPGA board, which has a maximum reliable clock frequency of 600MHz, and by the influence of the parasitic elements introduced by the PCB traces. In all measured cases an improvement of 2-4dB of the SFDR value has been obtained using the proposed calibration method.
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