Implementing the on-chip backpropagation learning algorithm on FPGA architecture

Scaling CMOS integrated circuit technology leads to decrease the chip price and increase processing performance in complex applications with re-configurability. Thus, VLSI architecture is a promising candidate in implementing neural network models nowadays. Backpropagation algorithm is used for training multilayer perceptron with high degree of parallel processing. Parallel computing implementation is the best suitable on FPGA or ASIC. The on-chip back-propagation learning algorithm design is proposed to implement 2×2×1 neural network architecture on FPGA. The simulation results show that back-propagation learning algorithm is converged in 3 epochs with error target as small as 0.05. The updated weighting also makes comparison between learning on FPGA and Matlab less than 2%. The achievements extend the applications with larger neural networks to communicate with other hardware architecture.