{"title":"可变2K/4K/ 8k点FFT/IFFT与紧凑的存储器，用于基于ofdm的DVB-T系统","authors":"J. Choi, Hui-Gon Kim, S. Han, S. Hwang","doi":"10.1109/ICSAI.2012.6223173","DOIUrl":null,"url":null,"abstract":"We Propose a 2K/4K/8K point FFT (Fast Fourier Transform) for OFDM (Orthogonal Frequency Division Multiplexing) of DVB-H (Digital Video Broadcast Terrestrial) Receiver. The proposed FFT architecture utilizes cascaded radix-4 single path feedback (SDF) structure based on the Radix-2/Radix-4 FFT algorithm.[11] We use block floating point scaling technique in order to increase SQNR. The 2K/8K FFT consists of 5 cascaded stages of radix-4 and 3 stages of radix-2 butterfly units. The SQNR of 58dB is achieved with 10-bit data input, 14-bit internal data and twiddle factors, and 18-bit data output. The core has 75,804 gates with 204,672 bits of RAM and 33,572 bits of ROM using 0.18um CMOS technology.","PeriodicalId":164945,"journal":{"name":"2012 International Conference on Systems and Informatics (ICSAI2012)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Variable 2K/4K/8K-point FFT/IFFT with compact memory for OFDM-based DVB-T system\",\"authors\":\"J. Choi, Hui-Gon Kim, S. Han, S. Hwang\",\"doi\":\"10.1109/ICSAI.2012.6223173\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We Propose a 2K/4K/8K point FFT (Fast Fourier Transform) for OFDM (Orthogonal Frequency Division Multiplexing) of DVB-H (Digital Video Broadcast Terrestrial) Receiver. The proposed FFT architecture utilizes cascaded radix-4 single path feedback (SDF) structure based on the Radix-2/Radix-4 FFT algorithm.[11] We use block floating point scaling technique in order to increase SQNR. The 2K/8K FFT consists of 5 cascaded stages of radix-4 and 3 stages of radix-2 butterfly units. The SQNR of 58dB is achieved with 10-bit data input, 14-bit internal data and twiddle factors, and 18-bit data output. The core has 75,804 gates with 204,672 bits of RAM and 33,572 bits of ROM using 0.18um CMOS technology.\",\"PeriodicalId\":164945,\"journal\":{\"name\":\"2012 International Conference on Systems and Informatics (ICSAI2012)\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Conference on Systems and Informatics (ICSAI2012)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSAI.2012.6223173\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Conference on Systems and Informatics (ICSAI2012)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSAI.2012.6223173","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Variable 2K/4K/8K-point FFT/IFFT with compact memory for OFDM-based DVB-T system
We Propose a 2K/4K/8K point FFT (Fast Fourier Transform) for OFDM (Orthogonal Frequency Division Multiplexing) of DVB-H (Digital Video Broadcast Terrestrial) Receiver. The proposed FFT architecture utilizes cascaded radix-4 single path feedback (SDF) structure based on the Radix-2/Radix-4 FFT algorithm.[11] We use block floating point scaling technique in order to increase SQNR. The 2K/8K FFT consists of 5 cascaded stages of radix-4 and 3 stages of radix-2 butterfly units. The SQNR of 58dB is achieved with 10-bit data input, 14-bit internal data and twiddle factors, and 18-bit data output. The core has 75,804 gates with 204,672 bits of RAM and 33,572 bits of ROM using 0.18um CMOS technology.
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