Yesung Kang, Jaewoo Kim, Sunmin Kim, S. Shin, Esan Jang, Jae Won Jeong, K. Kim, Seokhyeong Kang
{"title":"基于三进制CMOS紧凑模型的新型三进制乘法器","authors":"Yesung Kang, Jaewoo Kim, Sunmin Kim, S. Shin, Esan Jang, Jae Won Jeong, K. Kim, Seokhyeong Kang","doi":"10.1109/ISMVL.2017.52","DOIUrl":null,"url":null,"abstract":"Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design, we construct a standardternary-cell library and exploit a ternary static timing analysis(T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"A Novel Ternary Multiplier Based on Ternary CMOS Compact Model\",\"authors\":\"Yesung Kang, Jaewoo Kim, Sunmin Kim, S. Shin, Esan Jang, Jae Won Jeong, K. Kim, Seokhyeong Kang\",\"doi\":\"10.1109/ISMVL.2017.52\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design, we construct a standardternary-cell library and exploit a ternary static timing analysis(T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.\",\"PeriodicalId\":393724,\"journal\":{\"name\":\"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2017.52\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2017.52","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel Ternary Multiplier Based on Ternary CMOS Compact Model
Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design, we construct a standardternary-cell library and exploit a ternary static timing analysis(T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.