Tooled approach for formal verification of components interactions modeled in SysML

Software systems are becoming more complex and their implementation requires more rigorous modeling approaches, for this reason the OMG (Object Management Group) has implemented the SysML standard to model complex systems. Sequence diagram is one of the fundamental diagrams of SysML because it allows behavioral specification of systems. However, SysML still has a lack of formal semantics following his semi-formal definition, which makes it impossible to directly apply the simulation and verification methods to these diagrams. The model transformation community offers several solutions to transform the SysML specification into formal methods in order to bridge the gap between them, this community is divided into two principal’s axes, the first ones working on the formalization of structural diagrams, and the others have worked on behavioral diagrams. Our work contributes to behavioral modeling and aims to combine all the highlights of the other approaches in a single framework for formal verification of SDs, using TAN and Uppaal model checker. The proposed approach has been tested through a case study of an interaction between ATM and Bank to prove their reliability.