{"title":"CMOS晶体管输出级的最佳选择","authors":"A. López-Martín, R. Carvajal, J. Ramírez-Angulo","doi":"10.1109/ISCIT.2013.6645878","DOIUrl":null,"url":null,"abstract":"The optimal choice of output stages in CMOS transconductors in the presence of nonideal effects is analyzed. It is shown that current folding employing source-coupled differential pairs is advantageous versus the conventional approach based on current mirrors. Two versions of a CMOS transconductor, each one using one of the mentioned approaches, have been fabricated in a 0.5μm CMOS technology and tested. Measurement results confirm the linearity improvements of current folding at the output stage.","PeriodicalId":356009,"journal":{"name":"2013 13th International Symposium on Communications and Information Technologies (ISCIT)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"On the optimal choice of the output stage in CMOS transconductors\",\"authors\":\"A. López-Martín, R. Carvajal, J. Ramírez-Angulo\",\"doi\":\"10.1109/ISCIT.2013.6645878\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The optimal choice of output stages in CMOS transconductors in the presence of nonideal effects is analyzed. It is shown that current folding employing source-coupled differential pairs is advantageous versus the conventional approach based on current mirrors. Two versions of a CMOS transconductor, each one using one of the mentioned approaches, have been fabricated in a 0.5μm CMOS technology and tested. Measurement results confirm the linearity improvements of current folding at the output stage.\",\"PeriodicalId\":356009,\"journal\":{\"name\":\"2013 13th International Symposium on Communications and Information Technologies (ISCIT)\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 13th International Symposium on Communications and Information Technologies (ISCIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCIT.2013.6645878\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 13th International Symposium on Communications and Information Technologies (ISCIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCIT.2013.6645878","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On the optimal choice of the output stage in CMOS transconductors
The optimal choice of output stages in CMOS transconductors in the presence of nonideal effects is analyzed. It is shown that current folding employing source-coupled differential pairs is advantageous versus the conventional approach based on current mirrors. Two versions of a CMOS transconductor, each one using one of the mentioned approaches, have been fabricated in a 0.5μm CMOS technology and tested. Measurement results confirm the linearity improvements of current folding at the output stage.
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