Design of a dynamically reconfigurable architecture for the 3D image synthesis

In this paper, we present a dynamically reconfigurable (DR) architecture for a 3D image synthesis application. We address different issues not covered in similar works especially the use of low complex and cost FPGA and the simultaneous support of different constraints like the energy consumption and the real time constraint. The proposed system uses an adaptation module that monitors the internal architecture modifications using FPGA dynamic reconfiguration mechanism.