J. Jasielski, S. Kuta, W. Kołodziejski, W. Machowski
{"title":"基于STM32F407VGT6单片机和模拟DLL的混合LBDD PWM调制器用于数字类bd音频放大器","authors":"J. Jasielski, S. Kuta, W. Kołodziejski, W. Machowski","doi":"10.1109/MIXDES.2015.7208585","DOIUrl":null,"url":null,"abstract":"In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Hybrid LBDD PWM modulator for digital class-BD audio amplifier based on STM32F407VGT6 microcontroller and analog DLL\",\"authors\":\"J. Jasielski, S. Kuta, W. Kołodziejski, W. Machowski\",\"doi\":\"10.1109/MIXDES.2015.7208585\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.\",\"PeriodicalId\":188240,\"journal\":{\"name\":\"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2015.7208585\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2015.7208585","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hybrid LBDD PWM modulator for digital class-BD audio amplifier based on STM32F407VGT6 microcontroller and analog DLL
In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.