{"title":"H.264/AVC中四分之一像素运动估计的算法和体系结构","authors":"S. K. Chatterjee, I. Chakrabarti","doi":"10.1109/NCVPRIPG.2013.6776245","DOIUrl":null,"url":null,"abstract":"The present paper proposes a fast algorithm and its VLSI architecture for fast quarter pixel (QP) accurate motion estimation (ME). The proposed algorithm is based on the distribution of the QP motion vectors (MVs) around the half pixel MV. The proposed algorithm efficiently explores the most likely QP locations and therefore skips the unlikely ones. The number of QP search locations for the proposed algorithm is reduced by 50% compared to the original full search method but results in only about 0.12 dB peak signal to noise ratio degradation. The VLSI architecture of the proposed algorithm theoretically can process thirty three 1280×720 HDTV frames per second. The power consumption of the proposed architecture is also reduced by 15? compared to a recently reported architecture.","PeriodicalId":436402,"journal":{"name":"2013 Fourth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Algorithm and architecture for quarter pixel motion estimation for H.264/AVC\",\"authors\":\"S. K. Chatterjee, I. Chakrabarti\",\"doi\":\"10.1109/NCVPRIPG.2013.6776245\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The present paper proposes a fast algorithm and its VLSI architecture for fast quarter pixel (QP) accurate motion estimation (ME). The proposed algorithm is based on the distribution of the QP motion vectors (MVs) around the half pixel MV. The proposed algorithm efficiently explores the most likely QP locations and therefore skips the unlikely ones. The number of QP search locations for the proposed algorithm is reduced by 50% compared to the original full search method but results in only about 0.12 dB peak signal to noise ratio degradation. The VLSI architecture of the proposed algorithm theoretically can process thirty three 1280×720 HDTV frames per second. The power consumption of the proposed architecture is also reduced by 15? compared to a recently reported architecture.\",\"PeriodicalId\":436402,\"journal\":{\"name\":\"2013 Fourth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG)\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 Fourth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NCVPRIPG.2013.6776245\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Fourth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NCVPRIPG.2013.6776245","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Algorithm and architecture for quarter pixel motion estimation for H.264/AVC
The present paper proposes a fast algorithm and its VLSI architecture for fast quarter pixel (QP) accurate motion estimation (ME). The proposed algorithm is based on the distribution of the QP motion vectors (MVs) around the half pixel MV. The proposed algorithm efficiently explores the most likely QP locations and therefore skips the unlikely ones. The number of QP search locations for the proposed algorithm is reduced by 50% compared to the original full search method but results in only about 0.12 dB peak signal to noise ratio degradation. The VLSI architecture of the proposed algorithm theoretically can process thirty three 1280×720 HDTV frames per second. The power consumption of the proposed architecture is also reduced by 15? compared to a recently reported architecture.