用于宽带CDMA试验台的低功耗CMOS基带电路设计

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) Pub Date : 2000-07-26 DOI:10.1109/LPE.2000.155284

Chunlei Shi, Yue Wu, M. Ismail

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引用次数: 0

摘要

本文介绍了一种用于WCDMA直接转换接收机的CMOS基带电路的设计和性能。基带链由一个5阶抗混叠滤波器、一个4阶可调通道滤波器和三个可变增益放大器(VGA)级组成，提供72 dB增益范围和2 dB增益步长，可调谐以选择三种不同的带宽(从5 MHz到20 MHz射频间隔)。它从单个3V电源仅耗散18mw。输入IP3为10 dBm，通带输入参考噪声为41nV//spl径向/(Hz)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of a low-power CMOS baseband circuit for wideband CDMA testbed

In this paper, the design and performance of a CMOS base-band circuit for WCDMA direct conversion receiver are presented. Consisting of one 5th-order anti-aliasing filter, one 4th-order tunable channel filter, and three variable gain amplifier (VGA) stages, the baseband chain provides 72 dB gain range with 2 dB gain step and is tunable to select three different bandwidths (from 5 MHz to 20 MHz radio-frequency spacing). It dissipates only 18 mW from a single 3V supply. The input IP3 is 10 dBm, and the input-referred noise in the passband is 41nV//spl radic/(Hz).

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ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

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