{"title":"一个紧凑的8位AES加密处理器","authors":"F. Haghighizadeh, H. Attarzadeh, M. Sharifkhani","doi":"10.1109/ICCNT.2010.50","DOIUrl":null,"url":null,"abstract":"Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standard-cell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far.","PeriodicalId":135847,"journal":{"name":"2010 Second International Conference on Computer and Network Technology","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A Compact 8-Bit AES Crypto-processor\",\"authors\":\"F. Haghighizadeh, H. Attarzadeh, M. Sharifkhani\",\"doi\":\"10.1109/ICCNT.2010.50\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standard-cell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far.\",\"PeriodicalId\":135847,\"journal\":{\"name\":\"2010 Second International Conference on Computer and Network Technology\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Second International Conference on Computer and Network Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCNT.2010.50\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Second International Conference on Computer and Network Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCNT.2010.50","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standard-cell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far.
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