60 GHz Frequency Conversion 90 nm CMOS Circuits

This paper presents design and a characterisation of an active single-stage single-ended 30 to 60 GHz frequency doubler and a resistive down conversion mixer with differential buffer stage. These MMICs are realised using 90-nm CMOS process. The doubler exhibit 7.1 dB conversion loss and 10.8 dB fundamental frequency suppression with 0 dBm input power and 13.7 mW power consumption. Maximum output power of -4.2 dBm is achieved with 5 dBm input power. The mixer has 9.8 dB conversion gain with +5 dBm local oscillator level. The compression point P1dB is -2 dBm with 14 mW power consumption.