高性能超晶格冷级联的高效分段体器件

E. Siivola, P. Thomas, K. Coonley, A. Reddy, J. Posthill, B. Cook, R. Venkatasubramanian
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引用次数: 1

摘要

采用SiGe、PbTe和TAGS材料制备了分段体单偶联器件。最初的优化研究表明,发电效率超过12%,冷侧温度为/spl sim/175/spl℃,热侧温度为/spl sim/700/spl℃。目标是将这些器件级联到高性能Bi/sub 2/Te/sub 3/-超晶格冷级,工作温度在25/spl℃至175/spl℃之间。我们将讨论分段和级联组件之间的交易空间,因为它涉及到不同层之间的热和电匹配以及设备复杂性。它将显示层匹配如何影响整体器件性能,以及如何使用这些知识来确定最佳设计。我们还将讨论用于满足高温材料组装的各种挑战的方法,包括欧姆接触,扩散屏障和CTE诱导应力。将提供器件性能的测量结果,以说明所使用方法的后果。我们还将包括将这些两级分段器件早期集成到薄膜超晶格冷级器件以产生三级功率器件的结果。
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High efficiency segmented bulk devices cascaded with high-performance superlattice cold-stage
Segmented bulk single-couple devices have been fabricated using SiGe, PbTe, and TAGS materials. Initial optimization studies have yielded power generation efficiencies in excess of 12%, with cold-side temperatures of /spl sim/175/spl deg/C and hot-side temperatures of /spl sim/700/spl deg/C. The goal is to cascade these devices with high-performance Bi/sub 2/Te/sub 3/-superlattice cold-stage operating between 25/spl deg/C to 175/spl deg/C. We will be discussing the trade space between segmented and cascaded assemblies as it relates to the thermal and electrical matching between the different layers and device complexity. It will be shown how layer matching affects overall device performance and how this knowledge can be used to determine the optimal design. We will also discuss the methodologies used to meet the various challenges of high temperature materials assembly including ohmic contacts, diffusion barriers, and CTE induced stresses. Measurement results of device performance will be provided to illustrate the consequences of the methodologies used. We will also include results from early integration of these 2-stage segmented devices to thin-film superlattice cold-stage device to yield three stage power devices.
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