A graphical dataflow programming model for on-line signal processing on parallel architectures

Many real-world signal processing applications require an enormous amount of computational power. When these applications are deployed in on-line settings, many hurdles including stringent timing constraints must be overcome. Additionally, the number of channels feeding mathematical DSP routines is growing rapidly, easily reaching 1,000 to 100,000 channels. These applications have increasingly demanding performance requirements for generating control outputs which interact with real-world processes, where 1ms loop times are not uncommon. In this paper, we describe a graphical dataflow approach capable of yielding the necessary computational power and meeting aggressive timing constraints. We combine this methodology with strategies for targeting a combination of processors including CPUs, FPGAs, and GPUs deployed on standard PCs, workstations, and real-time systems. We demonstrate this approach through case studies on adaptive mirror control for an extremely large telescope and plasma measurement via soft X-ray tomography.