矩阵变换器正弦脉宽调制的FPGA实现

K. Vijayakumar, R. A. Kumar, A. Govindasamy, S. Kannan
{"title":"矩阵变换器正弦脉宽调制的FPGA实现","authors":"K. Vijayakumar, R. A. Kumar, A. Govindasamy, S. Kannan","doi":"10.1109/ICCSP.2014.6949971","DOIUrl":null,"url":null,"abstract":"The purpose of this paper is to develop the Sinusoidal Pulse Width Modulation (SPWM) for toggling the switches of Matrix Converter for its operation as several Power Electronics Converters. The SPWM generation is developed with the help of Quartus based Field Programmable Gate Array (FPGA). Quartus II is a software tool produced by Altera for analysis and synthesis of HDL design which enables the developer to compile their designs. Quartus II software includes all the design files, software source files and other related files necessary for the eventual implementation of a design in Programmable Logic Devices. SPWM provides a way to reduce the Total Harmonic Distortion (THD) of load current. The VHDL programming is used to generate the SPWM for switches. Simulation waveforms are obtained and the output of SPWM generation is developed with the help of the FPGA and the output is displayed in the CRO.","PeriodicalId":149965,"journal":{"name":"2014 International Conference on Communication and Signal Processing","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementation of Sinusoidal Pulse Width Modulation for Matrix Converter using FPGA\",\"authors\":\"K. Vijayakumar, R. A. Kumar, A. Govindasamy, S. Kannan\",\"doi\":\"10.1109/ICCSP.2014.6949971\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The purpose of this paper is to develop the Sinusoidal Pulse Width Modulation (SPWM) for toggling the switches of Matrix Converter for its operation as several Power Electronics Converters. The SPWM generation is developed with the help of Quartus based Field Programmable Gate Array (FPGA). Quartus II is a software tool produced by Altera for analysis and synthesis of HDL design which enables the developer to compile their designs. Quartus II software includes all the design files, software source files and other related files necessary for the eventual implementation of a design in Programmable Logic Devices. SPWM provides a way to reduce the Total Harmonic Distortion (THD) of load current. The VHDL programming is used to generate the SPWM for switches. Simulation waveforms are obtained and the output of SPWM generation is developed with the help of the FPGA and the output is displayed in the CRO.\",\"PeriodicalId\":149965,\"journal\":{\"name\":\"2014 International Conference on Communication and Signal Processing\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Communication and Signal Processing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCSP.2014.6949971\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Communication and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCSP.2014.6949971","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文的目的是开发正弦脉宽调制(SPWM),用于切换矩阵变换器的开关,使其作为多个电力电子变换器工作。SPWM生成是在基于Quartus的现场可编程门阵列(FPGA)的帮助下开发的。Quartus II是Altera生产的用于分析和合成HDL设计的软件工具,它使开发人员能够编译他们的设计。Quartus II软件包括在可编程逻辑器件中最终实现设计所需的所有设计文件、软件源文件和其他相关文件。SPWM提供了一种降低负载电流总谐波失真(THD)的方法。使用VHDL编程生成交换机的SPWM。得到仿真波形,利用FPGA开发SPWM生成输出,并在CRO中显示输出。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Implementation of Sinusoidal Pulse Width Modulation for Matrix Converter using FPGA
The purpose of this paper is to develop the Sinusoidal Pulse Width Modulation (SPWM) for toggling the switches of Matrix Converter for its operation as several Power Electronics Converters. The SPWM generation is developed with the help of Quartus based Field Programmable Gate Array (FPGA). Quartus II is a software tool produced by Altera for analysis and synthesis of HDL design which enables the developer to compile their designs. Quartus II software includes all the design files, software source files and other related files necessary for the eventual implementation of a design in Programmable Logic Devices. SPWM provides a way to reduce the Total Harmonic Distortion (THD) of load current. The VHDL programming is used to generate the SPWM for switches. Simulation waveforms are obtained and the output of SPWM generation is developed with the help of the FPGA and the output is displayed in the CRO.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Design and simulation of dense dielectric patch antenna for wireless applications Texture image retrieval by combining local binary pattern and discontinuity binary pattern Dynamic beacon based and load balanced geo routing in MANETs Analysis of leakage current and leakage power reduction during write operation in CMOS SRAM cell HDL implementation of 128- bit Fused Multiply Add unit for multi mode SoC
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1