Y. Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li
{"title":"用于三维集成电路的容错专用NoC拓扑综合","authors":"Y. Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li","doi":"10.1109/SOCC.2011.6085088","DOIUrl":null,"url":null,"abstract":"This paper proposes a synthesis methodology for constructing Application-Specific NoCs topology in 3D chips. The multi-cores and communications can be synthesized simultaneously in the system-level floorplanning process with fault tolerant consideration. As a result, the experimental results show that the proposed approach produces 3D NoCs with lower power dissipation than previous works in multimedia applications with relatively small overhead of the number of Through-Silicon-Vias (TSVs) for achieving 100% fault tolerance in 3D NoC links based on single fault assumption.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits\",\"authors\":\"Y. Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li\",\"doi\":\"10.1109/SOCC.2011.6085088\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a synthesis methodology for constructing Application-Specific NoCs topology in 3D chips. The multi-cores and communications can be synthesized simultaneously in the system-level floorplanning process with fault tolerant consideration. As a result, the experimental results show that the proposed approach produces 3D NoCs with lower power dissipation than previous works in multimedia applications with relatively small overhead of the number of Through-Silicon-Vias (TSVs) for achieving 100% fault tolerance in 3D NoC links based on single fault assumption.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085088\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085088","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits
This paper proposes a synthesis methodology for constructing Application-Specific NoCs topology in 3D chips. The multi-cores and communications can be synthesized simultaneously in the system-level floorplanning process with fault tolerant consideration. As a result, the experimental results show that the proposed approach produces 3D NoCs with lower power dissipation than previous works in multimedia applications with relatively small overhead of the number of Through-Silicon-Vias (TSVs) for achieving 100% fault tolerance in 3D NoC links based on single fault assumption.