Fast Verilog Simulation using Tel-based Verification Code Generation for Dynamically Reloading from Pre-Simulation Snapshot

As design complexity increases, turn-around time (TAT) of design development increases. Designers may not have enough time to cover all test, because Verilog simulation time increases. The aim of this paper is to present an existing Verilog simulation method and to propose a new method to reduce simulation run time for the design of large system implemented in Verilog in the iterative flows. Small changes in testbench caused the need to repeat all design flows, including basic and common test sequences such as booting and power on stabilization sequences. The proposed verification flows use the Tcl based verification code for dynamically reloading from previous simulation snapshot without repeated compiling of source code. The basic and commonly used long test sequences are saved by simulator using Tcl command and reload the saved snapshot after driving the test sequence using Tcl code without recompiling. The total simulation time was reduced by 53% with the proposed verification flow.