On the improved implementations and performance evaluation of digit-by-digit integer restoring and non-restoring cube root algorithms

This paper describes digit-by-digit integer restoring and non-restoring algorithms for computing the cube root of a 33-bit radicand and gives improved methods for the implementations of the algorithms to speed up the computations. The methods include calculating multiplication products in advance with additions and using carry save adders (CSAs) to calculate the partial remainder at each iteration. The cost/performance is evaluated by implementing the algorithms on an FPGA chip. The results show that the CSA methods achieve performance speedups of 199.63% and 177.06%, for restoring and non-restoring cube root algorithms, respectively.