一种带开关延迟线的光学后进出出缓冲器的改进设计

Xiaoliang Wang, Xiaohong Jiang, A. Pattavina
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引用次数: 1

摘要

光缓冲器的缺乏仍然是阻碍全光网络发展的主要问题之一。解决这个问题的一种方法是通过使用光开关和光纤延迟线(SDL)来模拟光缓冲器的行为。目前关于该主题的工作已经证明了构建基于sdl的先进先出(FIFO)缓冲区、优先级缓冲区等的可行性。后进先出(Last In First Out, LIFO)缓冲器是实现拥塞控制和QoS保证的另一个重要网络组件,为了高效设计这种光缓冲器,人们提出了并行和级联架构[1],[2]。最近在[3]中的工作表明,当M为偶数和奇数时,可以使用M光纤延迟线(FDLs)分别构建大小为B =(3/2)·2M/2−1和B = 2(M+1)/2−1的LIFO缓冲区。在本文中,我们改进了[3]中的工作,提供了一种更有效的基于sdl的光学LIFO缓冲器结构。我们首先证明了单级反馈结构由一个(M+1) × (M+1)交叉杆开关和M个fdl组成,将交叉杆的M个输出连接回M个输入,当M为偶数和奇数时,我们能够分别构建大小为B = 2·2M/2 - 2和B =(3/2)·2(M+1)/2 - 2的LIFO缓冲区。这是通过为每个FDL采用适当的延迟长度设置和在FDL之间仔细的数据包调度,以及利用FDL可以支持的同时读取和写入数据包的良好功能来实现的。我们进一步表明,如果我们采用一系列较小的开关而不是单个(M+1)×(M+1)大开关,就基本2 × 2开关元件的总数而言,新的LIFO设计可以以更低的复杂性实现。
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An improved design of optical LIFO buffer with switched delay lines
The lack of optical buffer is still one of the main problems that hinder the development of all optical networks. One approach to this problem is to emulate the behavior of optical buffers by using optical switches and fiber delay lines (SDL). Current works on this topic have demonstrated the feasibility of constructing SDL-based First In First Out (FIFO) buffer, Priority buffer, etc. The Last In First Out (LIFO) buffer is another important network component for congestion control and QoS guarantee, and parallel and cascade architectures have been peoposed for the efficient design of such optical buffer [1], [2]. The recent work in [3] showed that it is possible to use M fiber delay lines (FDLs) to construct a LIFO buffer of size B = (3/2) · 2M/2 − 1 and B = 2(M+1)/2 − 1 when M is even and odd, respectively. In this paper, we improve the work in [3] by providing a more efficient construction of SDL-based optical LIFO buffer. We first show that with a single stage feedback structure consisted of one (M + 1) × (M + 1) crossbar switch and M FDLs connecting M outputs of the crossbar back to M its inputs, we are able to construct a LIFO buffer of size B = 2 · 2M/2 − 2 and B = (3/2) · 2(M+1)/2 − 2 when M is even and odd, respectively. This is achieved through adopting a properly delay length setting for each FDL and a careful packets scheduling among FDLs, as well as exploiting the nice function of simultaneous packet reading and witting a FDL can support. We further show that if we adopt a cascade of smaller switches rather than a single (M+1)×(M+1) big switch, the new LIFO design can be implemented with much lower complexity in terms of the total number of basic 2 × 2 switch elements.
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