Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applications

With the current trend of the ever increasing detector coverage, more precise measurement results of an observed object in space are provided to the scientists. This trend implies also higher data rates and amount of data to be processed by Data Processing Units (DPUs). Classical ground processing steps need to be performed on-board of spacecrafts with the demand by the scientist to be adapted to mission specific requirement. With today high logic density SRAM-based FPGAs, proven solutions for space applications are provided and permit in-flight and dynamic partial reconfigurability in space. For such an enhanced system the system qualification has to be carefully considered to retain the achieved high reliability. With SEU induced errors and glitch effects during dynamic partial reconfiguration the system qualification in a bus-based architecture cannot be guaranteed. Therefore an enhanced architecture is required which provides guaranteed system qualification and supports a high performance DPU architecture. The Network-on-Chip (NoC) approach based SoCWire architecture has been developed to provide these enhanced design goals. This paper presents the SoCWire architecture verification, test and results for safe dynamic partial reconfiguration in space applications. Radiation induced errors and glitch-effects in SRAM-based FPGAs are described and the limitations of bus-based communication architectures are outlined. The NoC paradigm is introduced and its advantage for dynamic reconfigurable systems. The SoCWire architecture will be presented and results of the architecture verification are outlined.